Category: LITHOGRAPHY

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Rising Energy Burden Of Lithography

Lithography has become one of the most energy-intensive stages in the fabrication of wafers. As fabs push to 2 nm and below, every additional patterning layer increases electricity demand and associated CO₂ emissions. Industry projections now indicate that wafer-fab emissions will exceed approximately 270 Mt CO₂e by 2030, primarily from equipment-driven loads. Fabs cannot treat lithography power as a fixed cost anymore.

High-NA EUV, expected to be widely deployed in high-volume environments, delivers the resolution needed for advanced logic. However, it also increases per-tool power requirements, precisely the kind of “performance/energy ↑” tradeoff that sustainability teams are trying to mitigate. This imbalance is the reason lithography is now being singled out in sustainability roadmaps.

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What “Energy-Aware” Really Means

Energy-aware lithography integrates power consumption as a design and operational variable within the patterning process, alongside resolution, critical dimension control, and throughput. Instead of viewing electricity as a fixed cost, it measures kWh per wafer and CO₂ per layer as core performance metrics. Each exposure plan and dose setting is evaluated for both imaging fidelity and energy efficiency, shifting lithography from precision alone to precision with purpose.

At the fab level, energy awareness spans scanner design, standby control, and load balancing across exposure tools. It links process control with power management, allowing for the precise achievement of exact yield and overlay targets with reduced energy consumption. In this framework, sustainability becomes an engineered outcome rather than an afterthought.

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Emerging Data From Recent Research

Recent years have seen semiconductor research institutions and equipment makers quantify lithography’s energy and carbon footprint with far greater precision. This shift from broad sustainability targets to verifiable metrics such as energy per wafer, kilowatt-hours per layer, and carbon dioxide equivalent per exposure has redefined how efficiency is measured.

Organizations such as imec, ASML, and TSMC now publish data showing measurable progress in reducing power consumption across both process and equipment levels, aligning with the 2024 IRDS Environmental Chapter, which calls for quantifiable energy tracking throughout semiconductor manufacturing.

At the same time, policy frameworks such as NIST’s 2024 environmental assessment and SRC’s sustainability initiatives have recognized tool-level efficiency as a direct lever for emission reduction. This alignment between research, industry reporting, and regulatory guidance represents the first coordinated movement toward energy-transparent lithography, where every exposure and patterning decision is tied to a measurable energy outcome.

Recent studies from imec, ASML, and TSMC, supported by analyses such as Shintake (2024) on EUV power reduction and ElSayed et al. (2025) on carbon-per-transistor metrics, show a clear shift in how lithography energy is being addressed. The emphasis has moved from large facility upgrades to tool- and process-level optimization, where adaptive standby control, exposure planning, and dose tuning yield immediate reductions in power use.

Together, these works demonstrate that lithography energy is now a quantifiable engineering parameter. Integrating power metrics into process control and equipment specifications turns sustainability into a driver of performance, advancing the concept of truly energy-aware semiconductor manufacturing.

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Toward A Metric Of Energy Transparency

Latest developments across the industry have also highlighted a growing focus on the transparent reporting of lithography energy use. ASML has disclosed that its NXE:3600D EUV systems consume about 7.7 kilowatt-hours per exposed wafer pass, offering a concrete reference point for equipment-level efficiency.

IMEC’s modeling work indicates that lithography and etch together contribute over 40 percent of Scope 1 and 2 carbon emissions at advanced logic nodes, emphasizing where process-level optimization delivers the most significant impact. TSMC’s EUV Dynamic Power Saving Program further demonstrates operational transparency by achieving a 44 percent reduction in peak power and projecting 190 million kilowatt-hours in energy savings by 2030.

These examples collectively point toward a future where lithography energy is treated as a measurable parameter rather than an indirect cost. Adopting standard metrics, such as kilowatt-hours per exposure or carbon-equivalent per layer, would allow fabs and equipment suppliers to benchmark their performance and optimize power alongside yield and throughput.

Energy transparency at this level establishes efficiency as a shared engineering objective across the semiconductor ecosystem.

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Students And Computational Lithography

I recently wrote about computational lithography. Several students asked, apart from mathematics skills, what more is required to align educational training so one has a better chance of joining semiconductors as a computational lithography engineer. 

I thought a lot about this, and outlined in this blog are all the ins and outs of computational lithography that can benefit students.

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What Is Computational Lithography

Computational lithography, a critical component of the semiconductor manufacturing process, represents the intersection of computer science, physics, and engineering, tailored to enhance the capabilities of photolithography. Photolithography is a process used to transfer geometric patterns onto a substrate or silicon wafer, essential for creating the intricate circuits that form the backbone of electronic devices.

The field of computational lithography encompasses advanced algorithms and software tools to optimize this patterning process. Given the physical limitations of traditional lithography techniques, particularly as the semiconductor industry strives to shrink chip features to the sub-nanometer scale, computational lithography emerges as a pivotal solution. It enables the production of smaller, more efficient, and powerful microchips beyond the constraints of optical lithography.

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Why Learn About Computational Lithography

Learning computational lithography is becoming increasingly critical, especially within the semiconductor industry’s relentless drive toward miniaturization and efficiency improvement.

Several vital roles demand skills in computational lithography. Below is an example of a job description requiring computational lithography skills:

If as a student you are looking for more critical and technical reasons on why learning computational lithography is invaluable. Then below is a guide that can helpful.

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How To Learn And Enhance Skills Around Computational Lithography

Learning and enhancing skills in computational lithography involves a multidisciplinary approach, blending principles from physics, engineering, computer science, and mathematics. This field is crucial for those aspiring to contribute to the semiconductor industry’s evolution, particularly in designing and manufacturing ever-smaller and more efficient microchips.

Here’s a structured pathway to learn and enhance your skills in computational lithography:

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Photo by Dan Cristian Pădureț on Unsplash

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Computational lithography is a specialized field in the semiconductor manufacturing domain. It is used during lithography when advanced algorithmic models optimize the patterning and masking process. It is done by deforming the patterns to compensate for the physical and chemical effects naturally occurring in a standard flow. It utilizes the concept of inverse lithography to do so.

Result: Accurate production of the desired chip patterns on the wafer to fabricate the complex advanced node silicon.

Achieving such a complex and exact process on the go demands compute speed. It means that the equipment must either be equipped with high-performance XPUs to deliver a modeling approach or be able to offload and on load. In practice, the remote and distributed processing approach is better suited.

Performance: GPU-based inverse lithography enables performance speedup and thus helps generate accurate photomasks.

Efficiency: Advanced computational-based technique helps reduce the time to generate the mask.

However, as the complexity of the technology node increases, it has become challenging to keep up with the processing requirements of lithography. Thus, better XPUs and also software support is required.

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To tackle this bottleneck, NVIDIA, Synopsis, TSMC, and ASML have collaborated to leverage the software libraries on the GPU architectures. It will help drive silicon scaling and enable their end users to reduce costs and accelerate technology advancements. It leverages GPU-based inverse lithography.

Below is a simplified flow of what this collaboration will speed up further. Details around the litho library (cuLitho) were presented by Vivek K Singh, Vice President, Advanced Technology Group, NVIDIA, early this year.

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It is a significant step in the right direction when there is a proper set of collaborators: Covering GPU, EDA, Technology-Node, and Semiconductor Equipment experts.

Today, the compute workloads that achieve computational lithography are the most complex and extensive computational activity ever executed during semiconductor production.

Savings: Using next-gen XPUs help lower the cost of computational lithography due to the efficient processing.

Scaling: New computational lithography process continues the drive for further miniaturization of nodes.

With the latest advancements in GPU technology and the collaborative approach, computational lithography performance will skyrocket.

Eventually, semiconductor manufacturers will now achieve unprecedented speed and accuracy for all the lithography requirements. Such an improvement will also help drive better die-level manufacturing accuracy, improved yield, and the ability to continue to scale into the Angstrom era.

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