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THE MAJOR BLOCKS OF THE SEMICONDUCTOR FOUNDRY ROADMAP RACE

Semiconductor foundries across the globe are focused on providing solutions to retain existing customers and attract new customers. To achieve these two goals, semiconductor foundry companies have to keep innovating. Innovations are critical to ensure the solutions offered by foundries will spearhead the growth of new semiconductor products, thus the customers.

Semiconductor foundry roadmap plays a vital role in empowering customers with the future of semiconductor foundry technology. These roadmaps require years of research and development and are often in line with where the semiconductor industry is heading. Roadmaps also attract investors, and achieving roadmap milestones without delay is more important than ever. Any slip in achieving the milestones can directly impact customers and can derail market position.

The semiconductor foundries focus on several aspects of semiconductor technologies to drive semiconductor manufacturing forward. However, there are specific blocks that the majority of the semiconductor manufacturing players focus on as part of their long-term roadmap.

Technologies: Semiconductor foundries run on different types of semiconductor technologies. These semiconductor technologies are driven based on the product focus and capabilities of a given foundry. Semiconductor foundry fabricating only memory devices is more inclined towards (Example: Micron focuses on novel ways to increase layers of memory cells) providing memory-oriented semiconductor technologies. Similarly, analog, digital, or mixed-signal fabricating foundries focus on next-gen photo masking, etching, passivation, lithography, etc., to set their fabrication technology apart. The drive to focus on a specific technology (as per the foundry requirement) is the primary reason the yearly semiconductor roadmaps (from different companies) are focused on solutions that can enable future semiconductor technologies (devices, materials, etc.). Doing so can also expand the market share.

Devices: Devices are the basic building block of any silicon product. In the last few decades, the size of these devices (FETs) has only shrunk, thus providing more area to pack different types of processing blocks without utilizing a large silicon area. These devices have shrunk in size due to the massive research and development (between academia and industry) activities coupled with advancements in semiconductor equipment technology. Device research and development activities also need to be part of roadmaps to ensure next-gen solutions (like MBCFET, Next-Gen FinFET, etc.) cater to the requirements of both the foundries and the design houses.

End-Of-Line: Semiconductor fabrication requires three different lines/steps: Front, Middle, and Back. Front-End-Of-Line (FEOL) focuses on creating the structures that make the chip active as per the voltage and current requirements. Back-End-Of-Line (BEOL) process steps are primarily concerned with connecting different layers/blocks via complex interconnects. Lastly, to bridge the gap between the FEOL and BEOL, Middle-End-Of-Line (MEOL) is required. MEOL provides structures that serve as small contacts (like interconnects but have a specific and niche use/purpose during the fabrication) between different active regions of transistors. These three fabrication steps are the base of any silicon product. To keep up with Moore’s law, FEOL, MEOL, and BEOL have to be on the semiconductor foundry roadmaps so that every foundry can differentiate its process technologies from others and in the long term can provide unique solutions.

Materials: Similar to semiconductor devices, semiconductor materials also are one of the building blocks of semiconductor products. In reality, semiconductor products heavily utilize semiconductor materials during the manufacturing steps. The semiconductor foundry business will not exist without semiconductor materials like Silicon, Germanium, Gallium Arsenide, and several more. Apart from the basic periodic table materials, the semiconductor industry is also dependent on different kinds of chemicals. In the end, the semiconductor industry is built on top of basic science like any other industry is. Almost all semiconductor foundries focus on the materials aspect. However, given the slow change in new techniques around materials, the emphasis on semiconductor materials is not as big as any other aspect of semiconductor fabrication. Continuously improving the device efficiency means that the semiconductor foundries also need to focus on new types (Carbon nanotube, compound semiconductors, etc.) of materials to enable new solutions.

Automation: Semiconductor manufacturing (fabrication, assembly, and testing) is highly automated and requires minimal human interference to process the wafers. Semiconductor automation plays a vital role in ensuring that the lots get processed with the maximum throughput possible. Along the way, automation also captures/predicts issues that can empower semiconductor foundries with information to avoid delays and cost. The importance of automation has only grown in the semiconductor industry, and the dependency means automation technologies have become the default part of the semiconductor foundry roadmap.

Semiconductor foundries have focused on roadmaps for decades. It has helped them come up with next-gen technology and has also pushed the semiconductor technology race forward. Semiconductor Pure-Play Foundries and Integrated Device Manufacturers (IDM) are known for charting specific roadmaps that have always driven semiconductor manufacturing forward.

However, as the race to come up with the next-gen semiconductor manufacturing solutions grows, there is a need to focus on specific solutions that can push the manufacturing aspect of the semiconductor towards the angstrom era of devices.

THE NEW BLOCKS OF THE SEMICONDUCTOR FOUNDRY ROADMAP RACE

The continuous integration of new devices without increasing the silicon area has provided a new path for semiconductor design and manufacturing. Today, slim and compact electronics products are only possible due to the advent of a new class of semiconductor devices and technology-node that have ensured that the area required is not a hindrance to providing required power and performance.

Semiconductor researchers in collaboration with foundries have focused on several semiconductor technologies that have pushed the boundaries of semiconductor manufacturing so far. In the years to come, semiconductor foundries will need to focus on the new (examples below) building blocks of a roadmap for the semiconductor foundry.

FIN: The building blocks of semiconductor products are the devices. Until FinFET, these devices were planar. Starting with FinFET, the semiconductor design moved towards 2.5D. However, the need to scale further and put more transistors without compromising power and performance requires using 3D devices built using nanowire (GAAFET) and nanosheets (MBCFET). For increasing transistor density beyond Moore’s era, the semiconductor foundries will have to look into future devices that can utilize the FINs on the FET to drive the industry beyond 1nm and into the Angstrom era. It will require different foundries to focus heavily on a roadmap that purely focuses on developing new multi FIN-based FET devices.

xUV: Lithography is one of the critical fabrication process steps and also the costliest of all. Today, the most sophisticated UV technology to drive lithography is Extreme Ultraviolet (EUV). Only a handful of semiconductor foundries around the globe are capable of fabricating wafers using EUV equipment. The reason is the cost and also the fundamental issue like defects leading to reliability concerns. Technology like EUV is critical to meet semiconductor foundry’s technology-node goals. The semiconductor industry is on its way to surpass 2nm technology-node, which will require cost-effective and error-free lithography techniques that can enable devices transistors size of 1nm and beyond. It is only possible if semiconductor foundries work with semiconductor equipment manufacturers to drive a roadmap for next-gen lithography technology-powered equipment.

ABCD: Semiconductor foundries are fabricating hardware devices, but doing so requires several software solutions to keep the production line up and running apart from achieving the high yield, low defect, and faster throughput. All this is possible due to the focus on the ABCD (A = Artificial Intelligence, B = Big Data, C = Cloud, D = Digital Transformation) approach the semiconductor foundries have taken for a long time. As the world moves towards new semiconductor capacity, the need to drive next-gen ABCD solutions that are low on cost but high on efficiency will grow. Semiconductor foundries will have to keep innovating internally to ensure that the ABCD approach gets implemented via a roadmap to achieve the target (yield, scrapping, errors, etc.) results to drive minimal waste with maximum output.

Stacking: FinFETs tool the semiconductor industry from 2D devices to 2.5D devices. And today, the semiconductor industry is gearing to expand the FINs to enable the next-gen devices like CFET. CFET utilizes the folding approach to keep nFET on top of the pFET, thus securing the stacking approach for a real 3D integration. Stacking will also ensure that the next-gen devices utilize far less silicon area than today’s devices. It also requires innovation on the package-technology side, but the first step is always fabrication. Several device-level solutions exist that can transform horizontal integration into vertical. It will ensure the semiconductor industry keeps increasing the transistor density. However, there are still thermal, electrical, and failure (apart from cost) challenges that require a continuous improvement plan with the help of long term stacking roadmap.

Efficiency: Semiconductor products are defined based on how efficient they are. Efficiency does not mean low-power consumption but is about achieving the perfect balance of power, performance, and area (PPA) as per the target application. To achieve the balance of PPA, several semiconductor technological solutions from equipment, wafer size, devices, materials have to come together. Devices might be the most dominating aspect of achieving a balanced PPA. However, to fabricate these devices, different other semiconductor building blocks are required. Semiconductor foundries will have to have a roadmap that focuses on the power, performance, voltage, and area characteristics of the next-gen technology-node is at par with any given solution that exists today.

Several semiconductor manufacturing companies are gearing up to increase the worldwide installed semiconductor manufacturing capacity. However, increasing capacity is only half the job done. What is needed is the focus to keeps bringing new semiconductor manufacturing technologies that can excite the customer and drive the market towards a new era of semiconductor solutions.

The new upcoming semiconductor foundry capacity will require a semiconductor roadmap that drives new types of technology-node, equipment, automation, and other solutions. Semiconductor foundry’s roadmap from different competitors will ensure tomorrow’s semiconductor products are better than today’s and will also push the innovation around the products that semiconductor silicon devices are powering today and in the future.

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THE KNOWN SEMICONDUCTOR MANUFACTURING STRUGGLES

The cost of semiconductor manufacturing is doubling every four years. The major driving factor for the rising cost is the product complexity due to the introduction of new technology-node and packaging technologies. Electrical testing also has played a role in increased manufacturing costs due to the demand for advanced automated equipment.

All such costs are directly associated with the increase in transistor density with shrinking die area. The increase in transistor density has also lead to several semiconductor manufacturing struggles. These struggles (have been around for decades) are an indispensable part of the semiconductor manufacturing process.

Advanced and automated equipment often helps solve the unknown and known struggles. However, the demand to increase the number of lots processed per hour adds a constant pressure to ensure that every wafer/die/product that gets processed is using an error-free recipe.

While the semiconductor manufacturing process has numerous steps, some steps do require special attention to capture any issues before it leads to shipment of bad products/parts.

Defect: Fabricating, testing, and assembling thousands of dies often leads to defect. The defectivity rate is considerably low today than it was a few decades back. However, recipes are required to ensure that any wafer or assembled part is defect-free. Capturing defects is a manufacturing struggle, mainly due to the increasing layers/devices in the small silicon area. Sophisticated tools do capture defects, but a new type of defect can escape the fabrication scrutiny. Any such escape leads to known struggles of increase in processing time and cost.

Quality: Qualifying products is an important pillar of semiconductor product development. Depending on the product type, the qualification process has to follow standard steps before the product can be mass-produced. The industry standards do allow the easy flow of qualification. However, it is still a big struggle to ensure that all checks and processes get implemented correctly. As semiconductor products become more advanced, the cost and time associated with qualification (and failure analysis in case of part failure in the field) processes are rising. All this is pushing the qualification part of the semiconductor product development through the unknown to known struggles.

Data: Semiconductor and data go hand in hand. For decades, designers and manufacturers have spent a lot of time and effort to streamline a data-driven semiconductor product development process. However, as new advanced products get designed/manufactured, the cost of data capturing, analyzing, and storing is also rising. It is another struggle that the manufacturing process has to deal with. On the positive side, data today has become an integral part of semiconductor manufacturing, and so have been the tools to support data science activities to capture processes to defects. In the long run, the data struggle will keep increasing.

Break-Even: Cost of fabrication, testing, and assembly is rising. The capacity crunch is adding fuel to it. As new semiconductor technologies get launched, the cost of semiconductor manufacturing is rising. It also means that semiconductor manufacturers have to struggle their way through a long time before they can start earning net positive revenue. While this is true for several other manufacturing industries, the high CapEx that semiconductor manufacturing requires is very high and comes with risks.

Equipment: Every new semiconductor manufacturing technology (technology-node, package-technology, materials, chemicals, etc.) also pushes the need for a new type of equipment. It puts the FABs and OSATs through a continuous cycle of semiconductor manufacturing up-gradation, and also the equipment manufacturers, who have to struggle their way out to keep bringing new advanced equipment to drive next-gen semiconductor manufacturing technologies.

The above processes are just the handful of known struggles that any semiconductor product has to go through. Several sub-processes also exist and also require continuous monitoring to identify any known/unknown manufacturing issue.

Semiconductor manufacturing already has several recipes and equipment to ensure that the target number of lots is processed per hour, apart from ensuring that every wafer/part works as per the specification. However, to achieve such a goal also means to overcome several unknown issues that can show up during the semiconductor manufacturing process.

THE UNKNOWN SEMICONDUCTOR MANUFACTURING STRUGGLES

Apart from the known semiconductor manufacturing struggles, several unknown issues can pop up during semiconductor manufacturing (fabrication, testing, and assembly). These struggles are not like never seen before but remain classified as unknown due to the new information that is generated when such issues occur during the semiconductor manufacturing process.

Known Struggles: These struggles are part of the product by default, and a set process to capture issues around these processes already exists.

Unknown Struggles: These struggles are similar to known ones, but often through-off the product flow due to new issues that never existed before.

The time, cost, and efforts required to solve these unknown mysteries often impact the development cycle time. Any slip or late capturing of unknown issues can further increase the CapEx required to drive the product manufacturing and might put the semiconductor companies in tough spots.

Yield: Yield can make or break a semiconductor product. The data captured at every manufacturing step has a direct or indirect impact on the total yield. Yield issues, if any, are often based on several factors. While the majority of the yield issues can be solved without extra time/cost, there are often unknown issues that take up a lot of time and effort. As semiconductor manufacturing becomes complex (new devices), there will be unknown yield issues that will keep bringing unknown struggles.

Throughput: Keeping high uptime is a challenge for FABs and OSATs. However, there are often issues that are not known and can lead to lower throughput, and thus increases the cycle time of semiconductor product development. Throughput struggles are due to equipment downtime, new process testing, high demand, capacity crunch, and several other factors. The last two years have already shown how such unknown (high demand) throughput struggles are affecting the semiconductor supply chain.

Scheduling: Managing thousands of orders is a big challenge of semiconductor manufacturing. Scheduling techniques are used to ensure all the products/wafers are processed in a timely manner. Any unknown spike in demand or issue with any of the processes brings unknown scheduling challenges for the FABs and OSATs, and they often have to re-prioritize activities to ensure the cycle time does not increase for their customers. This is another unknown struggle semiconductor manufacturing has to often deal with.

Wafer Size: Every FAB and OSAT is defined based on the wafer size/capacity. There is a point wherein FABs and OSATs realize that the current wafer size/capacity is not enough. It implies FABs and OSATs now have to invest in new facilities, which brings an unknown challenge of whether the semiconductor manufacturing capacity should be based on new wafer size or should only be an expansion of current facilities (with same wafer size). The answers to these simple questions severely impact the future roadmap of any semiconductor manufacturing company and thus brings unknown planning and investment questions/struggles.

Handling: Materials are constantly moving in the FAB and also in the OSAT. Often the automated system used to drive material handling and processing go down, and several impacts material handling/processing. Such downtime of material handling brings unknown scheduling to processing challenges. It also often happens that the manual handling of materials leads to wafers getting scrapped, and this is another unknown variable that can occur anytime during semiconductor manufacturing.

Like any manufacturing industry, the semiconductor industry/manufacturing has to go through different phases of known and unknown struggles. These struggles do impact the time or the cost aspect of semiconductor manufacturing and often both.

In the last four to five decades, semiconductor manufacturing has seen several advances (technology to processes to facilities) that have only helped ease the manufacturing of semiconductor products. As the world moves towards more semiconductor-driven products and solutions, the hope is that new next-gen semiconductor manufacturing solutions (tools, equipment, data-driven approach, etc.) will lower the known and unknown semiconductor manufacturing struggles.

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THE HURDLES FOR THE SHRINKING SEMICONDUCTOR ROADMAP

Several roadmaps get initiated by different semiconductor companies and also semiconductor technical bodies. These roadmaps provided a path of where semiconductor technologies were, where it is today and where it will be tomorrow. In many cases, roadmaps also allow a way to understand how the product development phase will be for any given domain within the semiconductor industry or company.

These roadmaps are based on the capabilities of any given company to drive semiconductor technological innovation. These innovations then eventually push the industry towards the next-gen of solutions that set the path for future research and development. For example, the mass production of 2nm is heavily dependent on EUV technology, and when such a solution is used at a large scale then enables the development of more die-to-device-level optimization and research.

However, the continuous push to innovate and provide more balanced power and performance has now brought the semiconductor industry to a point where there are several challenges that companies (and the industry at large) need to overcome. These challenges will eventually enable new opportunities that will move the semiconductor product innovation ahead.

Configurability: The computing workloads in the 1990s were far less complex than the workloads today’s computing architectures are running today in the 2020s. For lighter workloads, a rigid IC (mainly XPUs) is perfect. Today, the workloads are changing due to the new data that gets generated faster than ever. That demands configurability from the lower level architecture to drive away any architectural bottlenecks. Configurability at the silicon level is all about adapting internal features based on the workload type. Configurability is hard to validate (apart from making it hack-proof), and the mass production of high-level configurable architecture remains a distant dream and a big challenge.

Bandwidth: Memory-intensive applications often require XPUs to read and write data to/from memory at a fast speed and that too at a high rate. Such continuous data movement is possible only if the memory bandwidth is large enough to drive faster data throughput. Theoretical maximum memory bandwidth overall has been increasing. It is mainly due to new XPUs that utilize memory interfaces via a high-bandwidth memory controller. There are applications (on the server-side) that require much larger bandwidth for faster GB/second to keep up with the read/write request from the processing unit. It is a challenge for semiconductor memory companies, as they gear up for the 5G+ and Edge computing world where every data point will have to get processed on the go.

Technology-Node: Research-driven design and development have enabled the shrinking of transistors. Today billions of transistors get fabricated in silicon chips to provide the highest performance possible. However, the race to pack more devices is now leading to a device scaling bottleneck. On top of that, device scaling is also pushing the boundaries of science (physics, chemistry, and math). The semiconductor industry is still marching ahead and is ready to touch the 1nm technology-node and then move to the angstrom era. The design and manufacturing challenges brought with the new device scaling era will be endless. The semiconductor industry will have to move beyond just focusing on the shrinking of the technology-node.

Package-Technology: The shrinking transistor size is not only affecting semiconductor manufacturing but also has impacted package-technology. The semiconductor industry has already found solutions by utilizing 2.5D/3D techniques as an avenue to drive next-gen package-technology. There are still thermal, mechanical, and electrical challenges that are not easy to solve with every growing silicon density. Today, disintegrated packaging solutions are being used to integrated different components to balance the device characteristics.

Interconnect: Any given silicon product has different blocks interconnected via different network topologies. Interconnect allows data movement and transfer between multiple processing units. The speed of the processing units itself drives the application response time. As the number of processing units has increased in XPU, managing the data traffic is becoming a challenge. The electrical interconnect is also leading to higher power consumption as the data traffic is increasing. Thus putting the semiconductor solutions to adopt for alternate techniques to drive next-gen interconnect. Optimizing other alternate interconnect (photonics) solutions is going to be a big challenge for XPU designers.

The semiconductor industry has followed the roadmap approach for a very long time. Such a continuous outlook has pushed the boundaries of semiconductor design and manufacturing. The roadmap is also the reason why several innovative semiconductor-powered solutions are coming out in the market. There are certainly challenges due to Moore’s law scaling down. However, these challenges are creating new opportunities and driving the semiconductor industry towards the More-Than-Moore era.

THE OPPORTUNITIES FOR THE SHRINKING SEMICONDUCTOR ROADMAP

The shrinking semiconductor challenges are also an opportunity for the semiconductor industry. These opportunities push the envelope of the semiconductor industry and thus create the roadmap for future technologies.

The growing need to pack more transistors using different processes or methods has provided the semiconductor industry to drive new design ideas. Several semiconductor design innovations have matured from the research stage and are being used to manufacture next-gen devices. The drive to provide a new optimized approach is opening up the future roadmap for the semiconductor industry.

These roadmaps are build by the opportunities created by the challenges that the industry faces today.

Chiplets: Increase in transistor density without increasing the silicon area leads to bottlenecks. These bottlenecks are not only around design (power and performance) but also on the manufacturing side. The manufacturing technologies (via technology-node and equipment support) have advanced to enable device fabrication at 2nm. The thermal, mechanical, and electrical characteristics (due to the small silicon area) are posing a challenge to the XPU design. Such challenges are also presenting a new opportunity for XPU designers. Semiconductor XPU design companies have now adopted the multi-die technique to spread the silicon area, which also has the potential to improve overall yield. AMD and Intel have already demonstrated XPUs with chiplets for multi-die XPUs, and will certainly dominate the market (in terms of design/innovation). 

Interposer: Chiplets manufacturing required the use of multiple dies. Connecting these different blocks to form an integrated chip/system often requires a specific silicon technology called interposer. Semiconductor companies often use different interposer terminology, but eventually, the underlying goal of each of these is to provide a common place for two or more die/blocks. Interposers usage will grow with the growth in chiplets adoptions. It also means providing optimized network-based topology to arrange/stack different blocks for efficiency, which is an opportunity for the research and development teams across academia and industry.

Wafer-Scale: Servers to supercomputers are getting faster every year. The need to shrink the data centers while not compromising on the throughput is pushing semiconductor design and manufacturing towards large-scale wafer-level solutions. For such solutions, the wafer-scale integration approach comes in as an opportunity to provide die areas as large as the wafer to create high-performance processing units. These units can then cater to any data demand of today and the future. Due to the advancement in semiconductor manufacturing, the yield at the wafer level will not be an issue, but the cost aspect can be.

Hybrid: Monolithic chips have been in use for several decades. Later, monolithic chips got replaced by multi-core homogeneous and heterogeneous architectures. As the world moves towards a more remote-enabled world, the need for multiple hybrid architectures will grow. These hybrid architectures will have unique processing characteristics, which will enable semiconductor design and manufacturing companies to leverage new methodologies like chiplets to heterogeneous architectures to mixing/matching IPs, thus providing an opportunity to expand the semiconductor roadmap.

One Package: System-In-A-Package (SiP) allows a way to integrate multiple systems under the same package technology (carrier package). Given the proliferation of multi-die integration, SiP will take the central stage. One package approach will allow semiconductor companies to provide a unified packaging approach to stick together different dies/IPs under the same substrate. While this will pose a challenge, the past success around similar package technology will smoothen this approach.

Continuous technology development is the key to ensuring that the semiconductor roadmap keeps moving forward. These new technological solutions also enable different industries that leverage the new design to manufacturing methodology to drive better customer experience.

As the semiconductor roadmap inches towards the 1nm era, it will be vital to keep innovating to move the world into the angstrom arena.

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THE REASONS FOR THE OVERLAPPING OF SEMICONDUCTOR PURE-PLAY FAB AND OSAT BUSINESS

Semiconductor manufacturing is heavily dependent on external vendors. This is more true for semiconductor companies that do not have any internal manufacturing capability and have to rely heavily on outsourcing.

This has made Pure-Play FAB and OSAT the two major driving forces of semiconductor manufacturing. It is widely known that FAB-LESS (and OSAT-LESS) semiconductor companies have contributed heavily in driving the external Pure-Play FAB and OSAT business.

There are few widely know accepted business model that defines the semiconductor design and manufacturing:

FAB-LESS: Semiconductor companies that only focus on semiconductor design and rely on external Pure-Play FAB and OSAT for semiconductor manufacturing.

IDM: Semiconductor companies that focus on both semiconductor design and manufacturing and have the internal capacity to execute both and also take help of external capacity when required.

Pure-Play FAB: Semiconductor companies that invest mainly in semiconductor fabrication capacity. Cater to both FAB-LESS and IDM.

OSAT: Outsourced semiconductor assembly and test business that caters to any semiconductor companies without internal assembly and testing capacity.

The above definitions were applicable in the 1980s and 1990s, and to some extent till the 2000s. However, as the reliance on the semiconductor industry has grown, so has the application of the above business models. This is at least true for Pure-Play FABs and OSATs because of the following reasons:

Opportunity: Both Pure-Play FABs (more than OSATs) and OSATs are seeing the growing importance of providing extensive services than only specific ones. This is pushing them towards each other’s market. Some of the big Pure-Play FABs already have internal assembly and testing facilities and are already capturing OSAT business. Few Pure-Play FABs are also forming JVs with external houses to provide OSAT services like an umbrella business. This is putting pressure on OSATs and slowly they have also started exploring opportunities beyond OSAT business itself.

Services: In the end, both Pure-Play FABs and OSATs are providing services to their customers. The more and the better services they can provide the larger market they can capture. Increasing portfolio and moving beyond dedicated services is another reason why Pure-Play FABs and OSATs are entering each other’s business market.

Technologies: Top Pure-Play FABs are already known for providing 2.5D/3D packaging expertise. This is mainly due to More-Than-Moore solutions the semiconductor world is looking forward to. This is naturally allowing Pure-Play FABs to increase back-end business, and thus putting pressure on OSAT to innovate its back-end solutions or provide Pure-Play FAB services to even out the market.

Resources: Both Pure-Play FABs and OSATs can drive new technological solutions from inception to production. The major factors are the internal resources (equipment, labs, facilities, etc.) and also a talented pool of researchers who can execute the new solutions on the go. This is another major reason why Pure-Play FABs and OSATs are looking at each other’s market and slowly rolling out new services.

New Model: The high cost to develop large FAB and OSAT to only provide one set of services is raising the question as to whether there is an opportunity to extend the same facility to drive new services. This eventually means providing overlapping services and thus enabling a new semiconductor business model.

Pure-Play FAB business started with the focus of providing big giant factories that can take design files and bring them to reality in form of silicon wafers. However, semiconductor fabrication is only one part (important though) of the semiconductor product development. Pre-fabrication and post-fabrication activities are also critical and Pure-Play FABs are realizing the importance of it, and to fill this gap, in the last few years Pure-Play FABs have started investing in assembly and testing services (design is not far behind). While this makes them essentially an Integrated Device Manufacturer (IDM), however, the percentage of assembly and testing services that Pure-Play FABs provides is still comparatively less but certainly on the rise.

OSAT business on other hand has primarily focused on assembly and testing, and it has allowed them to build high-class facilities that can test and package the product as per the customer requirements. However, as Pure-Play FABs start getting into the assembly and testing services, the OSAT business is changing itself to extend services beyond assembly and testing. Top OSATs are looking to invest in smaller FABs that can allow them to capture the fabrication market, and some OSATs have already created subsidiaries that focus on the design aspect of semiconductor product development. Thus also colluding with the FAB-LESS business model.

The overlapping of Pure-Play FAB and OSAT business is raising questions as to whether there even exists a specific semiconductor business model, and what are the long-term implications.

THE IMPLICATION OF MERGING SEMICONDUCTOR PURE-PLAY FAB AND OSAT BUSINESS

Semiconductor manufacturing companies expanding their business to provide more services is certainly a welcome move, but the implications of doing so can be both positive and negative. More so when Pure-Play FABs and OSATs extend their services and start capturing each other’s market.

For semiconductor customers (mainly FAB-LESS) having more options to outsource semiconductor manufacturing will be positive news only. However, only a handful of Pure-Play FAB is capable of capturing OSAT business, and this will certainly raise the level of dependence on big manufacturing giants which might not have positive implications in the long run.

This is why it is important to understand what are the major implications when Pure-Play FABs starts getting into the OSAT market and vice verse:

Competition: Overlapping of Pure-Play FABs and OSATs will increase the competition to provide semiconductor fabrication, testing, and assembly services. For customers hiring Pure-Play FAB and OSAT, it is a win-win situation and so will it be for the semiconductor industry at large as there will be more capacity and also options for outsourcing to semiconductor fabrication and back end services.

Dependence: If more semiconductor companies start providing fabrication to the assembly under one roof, then it will slowly make FAB-LESS more dependent (than today) on specific solutions providers. The major reason is due to the notion of keeping all semiconductor manufacturing under one location/flow so that the cycle time reduces. Hiring two different vendors brings more complexity than hiring a single vendor which can perform all the semiconductor manufacturing services at the same location.

Cost: If all the semiconductor manufacturing (fabrication, testing, and assembly) services are provided by a single entity, then it can allow semiconductor design companies to lower the cost by negotiating the terms. It might also be the case that the cost of development goes up due to new facilities requiring the full cycle of qualification before it can be used to fabrication, test, and assembly the silicon products.

Capacity: If Pure-Play FABs and OSATs ramp up their efforts to enter the new semiconductor manufacturing business, then it will bring new capacity for the semiconductor industry. In the long run, this can have a more positive impact and can certainly mitigate future semiconductor shortages.

Emerging Solutions: Extending business to provide new services often leads to innovation. This can very well happen if OSATs start exploring the fabrication business and drive newer technological solutions that are not only limited to technology nodes but are also about new semiconductor manufacturing methodologies. The same can be true for Pure-Play FABs.

The overlapping of Pure-Play FABs and OSATs is inevitable. One of the strategies that Pure-Play FABs and OSATs can deploy is to invest in smaller OSATs and FABs respectively. This can remove the risk of investing a large sum of money on upgrading existing facilities and can also bring life to smaller OSATs/FABs which are on the verge of closure.

In the end, if OSAT and Pure-Play FABs keeping increasing their foothold into each other’s arena, apart from trying hands on the semiconductor design (dominated by FAB-LESS and IDMs), then does that mean all OSAT and Pure-Play FABs will turn into IDMs and eventually there will be no dedicated OSAT and Pure-Pay FABs? Only time can answer this question.